I've been assigned to write the Flash memory Read/Write portion of a cooperative project in my Embedded Programming II course. The deliverable is a simple Nios II SOPC which reads and writes to Flash memory a byte at a time using the Altera DE2 Board. My approach was to use the DE2_Media_Computer modified to include the University Program Flash IP core. I modified the Media computer in the SOPC Builder, added the proper changes to Verilog top entity in Quartus II, and made the suggested timing constraint modifications. Everything generates and compiles without errors. According to the University IP Core documentation for Flash Memory, writing an -1 to the erase register should completely erase the Flash Memory. My brand new DE2 Board still has the Default Demo installed in Flash.

I wrote a short bit of C code to do just that. I compiled and loaded the code using the Monitor App. I then run the code, wait about 30secs and cycle power on the DE2.

The Default Demo is still there! I've obviously overlooked or over simplified something. Is there anyone out there who might be kind enough to look at my project and point my in the right direction?

May 23, 2017. Nicelabel Express 5 Keygen Music on this page. Altera University Program Flash Memory Demonstration. The HPS will be responsible for implement the PID algorithm. In Quartus, I will have 2 blocks in VHDL: one to read data from the ADC and send these data to HPS and the other block will be responsible for receive data from HPS and generate the. EE Times connects the global electronics community through news, analysis, education, and peer-to-peer discussion around technology, business, products and design.